The semiconductor industry has moved ever increasingly to copper conductive lines and interconnect structures in the construction of semiconductor devices. Copper has proven to be a very useful material. Especially, advantageous is the low resistivity relative to other comparable process materials (e.g., aluminum). As a result, copper circuitry suffers less from resistance-capacitance (RC) delays. This makes copper systems faster.
However, copper materials have the disadvantage of high diffusivity through dielectric and silicon materials on which the copper is deposited. This is especially problematic when copper is used with so-called low-K dielectric materials, which are coming into increasingly common usage. Diffusion of copper into insulating layers comprised of low-κ dielectric materials can result in serious problems. Diffusion of copper into low-κ materials degrades the dielectric performance of such materials and commonly leads to device failure. The industry has adapted to this problem by implementing a wide range of barrier layers to prevent the diffusion of copper into the affected materials. Typically, the barrier layers consist of thin layers of barrier material interposed between copper layers and low-κ dielectric layers.
Although such barrier layers are effective at preventing the diffusion of copper materials, such barrier layers suffer from their own set of difficulties. One such problem is that barrier layers can contribute to electromigration induced voiding in copper interconnect structures. Such voiding is a common source of circuit failure in copper based semiconductor structures. Such voiding is particularly problematic when it occurs in via structures. Research has shown that electromagnetic voiding is particularly common at the interface between the copper layer and the barrier layer.
This problem can be illustrated with reference to the schematic cross-section views illustrated in FIG. 1(a) and FIG. 1(b). In FIG. 1(a), a conventional multi-level semiconductor substrate 100 is depicted. A wafer surface is depicted with a copper line 104 formed therein. The copper line 104 is typically formed using copper or copper-containing materials (e.g., copper alloys or copper laminates and the like). Insulating layers 105, 106 comprised of electrically insulating material (e.g., SiO2, low-κ dielectrics, and other like materials) are formed on the wafer surface to provide dielectric insulation between metal lines and between layers. Other copper layers 107 are used to electrically interconnect the various layers of an IC through via or other electrical connection structures. In the depicted example, a copper layer 107 is formed in an opening formed in the insulating layer 105. The opening exposes underlying copper line 104. Such openings are commonly formed using damascene or dual-damascene fabrication processes. However, when copper is used in such processes, barrier layers are used to prevent copper from diffusing out of its intended location so that the copper does not “poison” the low-κ layers used in such semiconductor structures.
These barrier layers take the form of refractory metal barrier layers 110 and so-called dielectric barrier layers 111. Commonly, refractory metal barrier layers (metal barrier layers) 110 include refractory metals in their construction. Such refractory metal barrier materials can include tantalum (Ta) or titanium (Ti) based barrier materials (e.g., tantalum nitrides (TaN), tantalum silicon nitrides (TaSiN), or titanium nitrides (TiN)). Additionally, multi-layer refractory metal barrier layers can be formed. Also, graded metal barrier layers can be used.
Additionally, so-called dielectric barrier layers are used. Such dielectric barrier layers prevent copper diffusion but do not incorporate refractory metals in their construction. Typical examples of such dielectric barrier layers are formed of dielectric materials that include silicon carbide and silicon carbon nitride. Such materials generally have a relatively lower dielectric constant (κ) than the refractory metal barrier layers. However, it would be desirable to make use of dielectric barrier layers that have lower effective κ values.
Others have discovered that copper layer and line commonly include minute voids 108. Others have also discovered that during the ordinary operation of integrated circuit devices, copper atoms migrate within the copper lines 104 and layers 107. One of the unfortunate byproducts of such copper migration is that the voids 108 in the copper layers and lines also tend to migrate. Moreover, at certain points in such lines and layers the voids also tend to aggregate causing large “macrovoids” that can cause serious problems for circuit operation. If such macrovoids become large enough and form in the wrong locations they can and do cause circuit failure. One of the major pathways for such copper migration and macrovoid formation is at the interfaces between the copper layers (and lines) and the copper diffusion barrier layers (e.g., the metal and dielectric barrier layers).
FIG. 1(b) shows one of the problems circuits undergo when copper migration causes the voids 108 to move. In the depicted embodiment, the voids 108 have migrated and aggregated to form macrovoids 108′ that are large enough to cause the depicted interconnect structure to fail. As depicted, the aggregate size of the macrovoids 108′ can become quite sizable reducing current through regions having voids. As depicted, the problem becomes even worse when macrovoids 108′ migrate to narrow regions on in the semiconductor circuitry. As depicted in FIG. 1(b) a macrovoid 108′ has migrated to occlude the conduction pathway 103 (e.g., a via). In short, the macrovoid 108′ has migrated to the interface between the copper layer 107 (e.g., a via) and the metal line 104. Also, the macrovoid 108′ has grown so large that it destroys the current path between the copper layer 107 and the metal line 104. Moreover, such voiding problems are known to become worse when low κ materials are used. Current solutions to this problem require that a secondary via be constructed so that when one via fails a conduction path can still be achieved through the secondary via. Although such solutions work well enough for their intended purpose, improved solutions are desirable.